rev.pra 24/05/02 preliminary technical data preliminary technical data information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD7453/ad7443 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 pseudo differential, 600ksps, 12- & 10-bit adcs in 8-lead sot-23 features specified for v dd of 2.7 v to 5.25 v low power at max throughput rate: 3.75 mw typ at 1msps with v dd = 3 v 9 mw typ at 1msps with v dd = 5 v pseudo differential analog input wide input bandwidth: 70db sinad at 100khz input frequency flexible power/serial clock speed management no pipeline delays high speed serial interface - spi tm /qspi tm / microwire tm / dsp compatible power-down mode: 1a max 8 pin sot-23 and soic packages applications transducer interface battery powered systems data acquisition systems portable instrumentation motor control communications general description the AD7453/ad7443 are respectively 12- and 10-bit, low power, successive-approximation (sar) analog-to-digital converters that feature a pseudo differential analog input. these parts operate from a single 2.7 v to 5.25 v power supply and feature throughput rates up to 600ksps. the parts contains a low-noise, wide bandwidth, differen- tial track and hold amplifier (t/h) which can handle input frequencies in excess of 1mhz with the -3db point being 20mhz typically. the reference voltage is 2.5 v and is applied externally to the v ref pin. the conversion process and data acquisition are controlled using cs and the serial clock allowing the device to inter- face with microprocessors or dsps. the input signals are sampled on the falling edge of cs and the conversion is also initiated at this point. the sar architecture of these parts ensures that there are no pipeline delays. functional block diagram the AD7453/43 use advanced design techniques to achieve very low power dissipation at high throughput rates. product highlights 1.operation with 2.7 v to 5.25 v power supplies. 2.low power consumption. with a 3v supply, the AD7453/43 offer 3.75mw typ power consumption for 600ksps throughput. 3.pseudo differential analog input. the v in- input can be used as an offset from ground 4.flexible power/serial clock speed management. the conversion rate is determined by the serial clock, allowing the power to be reduced as the conversion time is reduced through the serial clock speed increase. these parts also feature a shutdown mode to maximize power efficiency at lower throughput rates. 5.no pipeline delay. 6.accurate control of the sampling instant via a cs input and once off conversion control. microwire is a trademark of national semiconductor corporation. spi and qspi are trademarks of motorola, inc. 12-bit successive approximation adc control logic AD7453/ ad7443 v in+ v in- v ref gnd sclk sdata c s v dd t/h
rev. pra preliminary technical data ?2? parameter test conditions/comments b version 1 unit dynamic performance signal to (noise + distortion) (sinad) 2 70 db min total harmonic distortion (thd) 2 -80db typ -75 db max peak harmonic or spurious noise 2 -82db typ -75 db max intermodulation distortion (imd) 2 second order terms -85 db typ third order terms -85 db typ aperture delay 2 10 ns typ aperture jitter 2 50 ps typ full power bandwidth 2 @ -3 db 20 mhz typ @ -0.1 db 2.5 mhz typ dc accuracy resolution 12 bits integral nonlinearity (inl) 2 1 lsb max differential nonlinearity (dnl) 2 guaranteed no missed codes to 12 bits. 1 lsb max offset error 2 3 lsb max gain error 2 3 lsb max analog input full scale input span v in+ - v in- v ref v absolute input voltage v in+ v ref v v in- 3 0.1 to 1 v dc leakage current 1 a max input capacitance when in track 20 pf typ when in hold 6 pf typ reference input v ref input voltage 1% tolerance for specified performance 2.5 v dc leakage current 1 a max v ref input capacitance 15 pf typ logic inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current, i in typically 10na, v in = 0vorv dd 1 a max input capacitance, c in 4 10 pf max logic outputs output high voltage, v oh v dd = 5v; i source = 200a 2.8 v min v dd = 3v; i source = 200a 2.4 v min output low voltage, v ol i sink =200a 0.4 v max floating-state leakage current 1 a max floating-state output capacitance 4 10 pf max output coding straight (natural) binary AD7453 - specifications 1 ( v dd = 2.7v to 5.25v, f sclk = 12mhz, f s = 600ksps, v ref = 2.5 v; f in = 100khz; t a = t min to t max , unless otherwise noted.)
rev. pra preliminary technical data ?3? AD7453/ad7443 parameter test conditions/comments b version 1 units conversion rate conversion time 1.3s with a 12mhz sclk 16 sclk cycles track/hold acquisition time 2 sine wave input 200 ns max step input t b d t b d ns max throughput rate 6 600 ksps max power requirements v dd 2.7/5.25 vmin/max i dd 5,7 normal mode(static) sclk on or off 0.5 ma typ normal mode (operational) v dd = 5 v. 1.8 ma max v dd = 3 v. 1.25 ma max full power-down mode sclk on or off 1 a max power dissipation normal mode (operational) v dd =5 v. 9 mw max v dd =3 v. 3.75 mw max full power-down v dd =5 v. sclk on or off 5 w max v dd =3 v. sclk on or off 3 w max notes 1 temperature ranges as follows: b versions: ?40c to +85c. 2 see ?terminology? section. 3 a small dc input is applied to v in- to provide a pseudo ground for v in+ 4 sample tested @ +25c to ensure compliance. 5 see power versus throughput rate section. 6 see ?serial interface section?. 7 measured with a midscale dc input. specifications subject to change without notice. AD7453 - specifications 1
rev. pra preliminary technical data ?4? parameter test conditions/comments b version 1 unit dynamic performance signal to (noise + distortion) (sinad) 2 61 db min total harmonic distortion (thd) 2 -80db typ -73 db max peak harmonic or spurious noise 2 -82db typ -73 db max intermodulation distortion (imd) 2 second order terms -78 db typ third order terms -78 db typ aperture delay 2 10 ns typ aperture jitter 2 50 ps typ full power bandwidth 2 @ -3 db 20 mhz typ @ -0.1 db 2.5 mhz typ dc accuracy resolution 10 bits integral nonlinearity (inl) 2 0.5 lsb max differential nonlinearity (dnl) 2 guaranteed no missed codes to 10 bits. 0.5 lsb max offset error 2 3 lsb max gain error 2 3 lsb max analog input full scale input span v in+ - v in- v ref v absolute input voltage v in+ v ref v v in- 3 0.1 to 1 v dc leakage current 1 a max input capacitance when in track 20 pf typ when in hold 6 pf typ reference input v ref input voltage 1% tolerance for specified performance 2.5 v dc leakage current 1 a max v ref input capacitance 15 pf typ logic inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current, i in typically 10na, v in = 0vorv dd 1 a max input capacitance, c in 4 10 pf max logic outputs output high voltage, v oh v dd = 5v; i source = 200a 2.8 v min v dd = 3v; i source = 200a 2.4 v min output low voltage, v ol i sink =200a 0.4 v max floating-state leakage current 1 a max floating-state output capacitance 4 10 pf max output coding straight (natural) binary ad7443 - specifications 1 ( v dd = 2.7v to 5.25v, f sclk = 12mhz, f s = 600ksps, v ref = 2.5 v; f in = 100khz; t a = t min to t max , unless otherwise noted.)
rev. pra preliminary technical data ?5? AD7453/ad7443 parameter test conditions/comments b version 1 units conversion rate conversion time 1.3s with a 12mhz sclk 16 sclk cycles track/hold acquisition time 2 sine wave input 200 ns max step input t b d ns max throughput rate 6 600 ksps max power requirements v dd 2.7/5.25 vmin/max i dd 6,7 normal mode(static) sclk on or off 0.5 ma typ normal mode (operational) v dd = 5 v. 1.8 ma max v dd = 3 v. 1.25 ma max full power-down mode sclk on or off 1 a max power dissipation normal mode (operational) v dd =5 v. 9 mw max v dd =3 v. 3.75 mw max full power-down v dd =5 v. sclk on or off 5 w max v dd =3 v. sclk on or off 3 w max notes 1 temperature ranges as follows: b versions: ?40c to +85c. 2 see ?terminology? section. 3 a small dc input is applied to v in- to provide a pseudo ground for v in+ 4 sample tested @ +25c to ensure compliance. 5 see power versus throughput rate section. 6 see ?serial interface section?. 7 measured with a midscale dc input. specifications subject to change without notice. ad7443 - specifications 1
rev. pra preliminary technical data ?6? limit at parameter t min , t max units description f sclk 4 10 khz min 12 mhz max t convert 16 x t sclk t sclk = 1/f sclk 1.3 s max t quiet 25 ns min minimum quiet time between the end of a serial read and the next falling edge of cs t 1 10 ns min minimum cs pulsewidth t 2 10 ns min cs falling edge to sclk falling edge setup time t 3 5 20 ns max delay from cs falling edge until sdata 3-state disabled t 4 5 40 ns max data access time after sclk falling edge t 5 0.4 t sclk ns min sclk high pulse width t 6 0.4 t sclk ns min sclk low pulse width t 7 10 ns min sclk edge to data valid hold time t 8 6 10 ns min sclk falling edge to sdata 3-state enabled 35 ns max sclk falling edge to sdata 3-state enabled t power-up 7 1 s max power-up time from full power-down notes 1 sample tested at +25c to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 volts. 2 see figure 1, figure 2 and the ?serial interface? section. 3 common mode voltage. 4 mark/space ratio for the sclk input is 40/60 to 60/40. 5 measured with the load circuit of figure 3 and defined as the time required for the output to cross 0.8 v or 2.4 v with v dd = 5 v and time for an output to cross 0.4 v or 2.0 v for v dd = 3 v. 6 t 8 is derived from the measured time taken by the data outputs to change 0.5 v when loaded with the circuit of figure 2. the meas ured num- ber is then extrapolated back to remove the effects of charging or discharging the 50 pf capacitor. this means that the time, t 8 , quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 7 see ?power-up time? section. specifications subject to change without notice. timing specifications 1,2 ( v dd = 2.7v to 5.25v, f sclk = 12mhz, f s = 600ksps, v ref = 2.5 v; f in = 100khz; t a = t min to t max , unless otherwise noted.) figure 1. AD7453 serial interface timing diagram figure 2.ad7443 serial interface timing diagram 1 2345 13 16 15 14 t 3 00 0 0 db9 db8 db0 0 0 t 2 4 leading zero?s 3-state t 4 t 6 t 5 t 7 t 8 t quiet convert t b c s sclk sdata t 1 2 trailing zeros 1 2345 13 16 15 14 t 3 00 0 0 db11 db10 db2 db1 db0 t 2 4 leading zero?s 3-state t 4 t 6 t 5 t 7 t 8 t quiet convert t b c s sclk sdata t 1 AD7453/ad7443
rev. pra preliminary technical data ?7? AD7453/ad7443 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD7453/ad7443 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings 1 (t a = +25c unless otherwise noted) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . -0.3 v to +7 v v in+ to gnd . . . . . . . . . . . . . . . . . ?0.3 v to v dd + 0.3 v v in- to gnd . . . . . . . . . . . . . . . ?0.3 v to v dd + 0.3 v digital input voltage to gnd . . . . . . . . -0.3 v to +7 v digital output voltage to gnd . -0.3 v to v dd + 0.3 v v ref to gnd . . . . . . . . . . . . . . . . . -0.3 v to v dd +0.3 v input current to any pin except supplies 2 . . . . 10ma operating temperature range commercial (a, b version) . . . . . . . . . -40 o c to +85 o c storage temperature range . . . . . . . . . -65 o c to +150 o c junction temperature . . . . . . . . . . . . . . . . . . . . . . . +150 o c u ja thermal impedance . . . . . . . . . . 205.9c/w (soic) 211.5c/w (sot-23) u jc thermal impedance . . . . . . . . . 43.74c/w (soic) 91.99c/w (sot-23) lead temperature, soldering vapor phase (60 secs) . . . . . . . . . . . . . . . . . . . +215 o c infared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . +220 o c esd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.5kv notes 1 stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 transient currents of up to 100 ma will not cause scr latch up. linearity package model range error ( lsb) 1 option 4 branding information AD7453brt -40c to +85c 1 lsb rt-8 tbd AD7453brm -40c to +85c 1 lsb rm-8 tbd ad7443brt -40c to +85c 0.5 lsb rt-8 tbd ad7443brm -40c to +85c 0.5 lsb rm-8 tbd tbd evaluation board eval-control brd2 3 controller board ordering guide notes 1 linearity error here refers to integral non-linearity error. 2 this can be used as a stand-alone evaluation board or in conjunction with the evaluation board controller for evaluation/demons tration purposes. 3 evaluation board controller. this board is a complete unit allowing a pc to control and communicate with all analog devices evaluation boards ending in the cb designators. to order a complete evaluation kit, you will need to order the adc evaluation b oard i.e. tbd, the eval-control brd2 and a 12v ac transformer. see the tbd technote for more information. 4 rt = sot-23; rm = soic figure 3. load circuit for digital output timing specifications +1.6v i ol 200a 200a i oh to ou tp ut pin c l 50 pf
rev. pra preliminary technical data ?8? AD7453/ad7443 pin configuration soic pin function description pin mnemonic function v ref reference input for the AD7453/43. an external 2.5 v reference must be applied to this input.this pin should be decoupled to gnd with a capacitor of at least 0.1f. v in+ non-inverting input. v in- inverting input. this pin sets the ground reference point for the v in+ input. connect to ground or to a small dc offset to provide a pseudo ground. g n d analog ground. ground reference point for all circuitry on the AD7453/43. all analog input signals and any external reference signal should be referred to this gnd voltage. cs chip select. active low logic input. this input provides the dual function of initiating a conversion on the AD7453/43 and framing the serial data transfer. sdata serial data. logic output. the conversion result from the AD7453/43 is provided on this out put as a serial data stream. the bits are clocked out on the falling edge of the sclk input. the data stream of the AD7453 consists of four leading zeros followed by the 12 bits of conversion data which are provided msb first; the data stream of the ad7443 consists of four leading zeros, followed by the 10-bits of conversion data, followed by two trailing zeros. in both cases, the output coding is straight (natural) binary. sclk serial clock. logic input. sclk provides the serial clock for accessing data from the part. this clock input is also used as the clock source for the conversion process. v dd power supply input. v dd is 2.7 v to 5.25 v. this supply should be decoupled to gnd with a 0.1f capacitor and a 10f tantalum capacitor. pin configuration 8-lead sot-23 AD7453/ad7443 sot-23 (not to scale) top view 1 2 3 4 5 6 7 8 v ref v in+ v in- gnd c s sdata sclk v dd AD7453/ad7443 soic (not to scale) top view 1 2 3 4 5 6 7 8 v ref v in+ v in- gnd c s sdata sclk v dd
rev. pra preliminary technical data ?9? AD7453/ad7443 terminology signal to (noise + distortion) ratio this is the measured ratio of signal to (noise + distortion) at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. the theoretical signal to (noise + distortion) ratio for an ideal n-bit con- verter with a sine wave input is given by: signal to ( noise + distortion ) = (6.02 n + 1.76) db thus for a 12-bit converter, this is 74 db and for a 10-bit converter this is 62db. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the fundamental. for the ad7450, it is defined as: thd (db ) = 20 log v 2 2 + v 3 2 + v 4 2 + v 5 2 + v 6 2 v 1 where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 and v 6 are the rms amplitudes of the second to the sixth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it will be a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. intermodulation distortion terms are those for which neither m nor n are equal to zero. for example, the second order terms in- clude (fa + fb) and (fa C fb), while the third order terms include (2fa + fb), (2fa C fb), (fa + 2fb) and (fa C 2fb). the AD7453/43 is tested using the ccif standard where two input frequencies near the top end of the input band- width are used. in this case, the second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. as a result, the second and third order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification where it is the ratio of the rms sum of the individual dis- tortion products to the rms amplitude of the sum of the fundamentals expressed in dbs. aperture delay this is the amount of time from the leading edge of the sampling clock until the adc actually takes the sample. aperture jitter this is the sample to sample variation in the effective point in time at which the actual sample is taken. full power bandwidth the full power bandwidth of an adc is that input fre- quency at which the amplitude of the reconstructed fundamental is reduced by 0.1db or 3db for a full scale input. integral nonlinearity (inl) this is the maximum deviation from a straight line pass- ing through the endpoints of the adc transfer function. differential nonlinearity (dnl) this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error this is the deviation of the first code transition (000...000 to 000...001) from the ideal (i.e. agnd + 1lsb) gain error this is the deviation of the last code transition (111...110 to 111...111) from the ideal (i.e., v ref - 1lsb), after the offset error has been adjusted out. track/hold acquisition time the track/hold amplifier returns into track mode on the 13th sclk rising edge (see the serial interface sec- tion). the track/hold acquisition time is the minimum time required for the track and hold amplifier to remain in track mode for its output to reach and settle to within 0.5 lsb of the applied input signal. power supply rejection ratio (psrr) the power supply rejection ratio is defined as the ratio of the power in the adc output at full-scale frequency, f, to the power of a 200mv p-p sine wave applied to the adc v dd supply of frequency fs. the frequency of this input varies from 1khz to 1mhz. psrr (db) = 10 log (pf/pfs) pf is the power at frequency f in the adc output; pfs is the power at frequency fs in the adc output.
rev. pra preliminary technical data ?10? AD7453/ad7443 serial interface figures 1 and 2 show detailed timing diagrams for the serial interface of the AD7453 and the ad7443 respec- tively. the serial clock provides the conversion clock and also controls the transfer of data from the device during conversion. cs initiates the conversion process and frames the data transfer. the falling edge of cs puts the track and hold into hold mode and takes the bus out of three- state. the analog input is sampled and the conversion initiated at this point. the conversion will require 16 sclk cycles to complete. once 13 sclk falling edges have occurred, the track and hold will go back into track on the next sclk rising edge as shown at point b in figures 1 and 2. on the 16th sclk falling edge the sdata line will go back into three-state. if the rising edge of cs occurs before 16 sclks have elapsed, the conversion will be terminated and the sdata line will go back into three-state on the 16th sclk falling edge. the conversion result from the AD7453/43 is provided on the sdata output as a serial data streatm. the bits are clocked out on the falling edge of the sclk input. the data streatm of the AD7453 consists of four leading zeros, followed by 12 bits of conversion data which is provided msb first; the data stream of the ad7443 consists of four leading zeros, followed by the 10 bits of conversion data, followed by two trailing zeros, which is also provided msb first. in both cases, the output coding is straight (natural) binary. 16 serial clock cycles are required to perform a conversion and to access data from the AD7453/43. cs going low provides the first leading zero to be read in by the micro- controller or dsp. the remaining data is then clocked out on the subsequent sclk falling edges beginning with the second leading zero. thus the first falling clock edge on the serial clock provides the second leading zero. the final bit in the data transfer is valid on the 16th falling edge, having been clocked out on the previous (15th) falling edge. in applications with a slower sclk, it may be possible to read in data on each sclk rising edge i.e. the first rising edge of sclk after the cs falling edge would have the leading zero provided and the 15th sclk edge would have db0 provided.
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